1. Field of the Disclosure
The present invention relates to electronic devices, and more particularly, to electronic devices having nonvolatile memory.
2. Description of the Related Art
Conventional memory arrays include pluralities of individual memory cells. The memory cells can be programmed for desired logic or memory states. When programmed, each cell of the memory array will have a program state that represents either a high or low signal (i.e., on or off) during a read operation. Memories having cells that maintain their programmed state when powered down are referred to as nonvolatile memories.
Nonvolatile memories are organized into one or more nonvolatile memory (NVM) arrays organized by rows and columns. Typically, the rows of an NVM array are referred to as being along wordlines and the columns of the array are referred to as being along bitlines, although this definition is arbitrary depending on the physical orientation of the array. The method of reading the individual memory cells from a NVM array may vary and may determine the NVM architecture. There are two commonly used NVM architectures: a NOR architecture and a NAND architecture. In both NVM architectures the wordlines are able to change the on/off state of all memory cells on a specified row. The information of a specific memory cell of the NVM array can be determined by measuring the current in the column (bitline) containing this memory cell, referred to as the selected column, while adjusting the wordline potential of the row containing this memory cell, referred to as the selected row, relative to the wordline potentials of the other rows, referred to as the unselected rows. In such a manner the conductivity of a specified cell can be determined by measuring the current flowing into or out of the selected column.
For a NOR architecture, the memory cells within a given column are connected in parallel so that current can flow into, or out of, the column if any memory cell in the given column is conducting. For the NOR architecture, the wordline potentials of unselected rows are adjusted to limit the current flowing through memory cells connected to the unselected rows, e.g., current flowing into or out of the column, regardless of their state, to allow the state of a memory cell in the selected row to be detected
For a NAND memory architecture the memory cells within a given column are connected in series. Therefore, for current to conduct through the column all memory cells within a given column must be conducting. To inspect the information held within a specified memory cell of a NAND architecture, the wordlines of unselected rows are set to a value so that the memory cells of unselected rows are sufficiently conducting to determine the conductivity of the memory cell in the selected row for some specified selected row wordline potential.
Those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.